1. Technical Field
The present invention relates to semiconductor circuits in general, and in particular to domino logic circuits. Still more particularly, the present invention relates to a compound domino logic circuit having output noise elimination.
2. Description of the Prior Art
A domino logic circuit simplifies digital logic by connecting a number of transistors together in series to implement digital combination logic. For example, a domino logic circuit implements a logic AND function by cascading a p-channel transistor with several n-channel input transistors in series between a power supply and ground. During operation, the p-channel transistor is clocked to precharge an output node of the circuit to a predetermined logic state. Depending on the logic state at the inputs of the n-channel input transistors, the output node either remains at its precharged state or is pulled low through the series of n-channel input transistors connected to ground.
It is quite common for logic gates, such as AND, OR, and their combinations, in certain high performance logic control circuits to have a large number of inputs. However, due to current technology limitations, it is impractical to stack more than four input transistors in a simple domino logic circuit configuration for supporting a large number of inputs; hence typically, a compound domino logic circuit structure having a large fan-in is utilized instead. Due to the size and the stacked configuration of the p-channel transistors at the output of a compound domino logic circuit, a charge sharing problem may occur at the nodes between the p-channel transistors. Consequently, it is desirable to provide a solution to the charge sharing problem in a compound domino logic circuit without adding noise to the output.